Ⅰ 用Verilog語言怎麼寫一個60進制的計數器然後顯示在數碼管上
mole xue3(iSW,oHEX3,oHEX2,oHEX1,oHEX0);
input [3:0] iSW;
output oHEX3,oHEX2,oHEX1,oHEX0;
//下面點亮四個七段數碼管
bcd7seg digit0(iSW[3:0],oHEX0);
bcd7seg digit1(iSW[3:0],oHEX1);
bcd7seg digit2(iSW[3:0],oHEX2);
bcd7seg digit3(iSW[3:0],oHEX3);
endmole
//下面是子模塊。歡~~迎~~加fpga~qun~~37378637 /////////////
mole bcd7seg(B,H);
input [3:0] B;
output reg H;
always @(B) begin
case (B) //選擇輸出數據，這里採用的是共陽極接法,要是共陰極各數按位全部取反即可。從最低位開始分別代表了七段中的abcdefg第8位是D.P段
4'h0: H = 8'hc0; //顯示0
4'h1: H = 8'hf9; //顯示1
4'h2: H = 8'ha4; //顯示2
4'h3: H = 8'hb0; //顯示3
4'h4: H = 8'h99; //顯示4
4'h5: H = 8'h92; //顯示5
4'h6: H = 8'h82; //顯示6
4'h7: H = 8'hf8; //顯示7
4'h8: H = 8'h80; //顯示8
4'h9: H = 8'h90; //顯示9
4'ha: H = 8'h88; //顯示a
4'hb: H = 8'h83; //顯示b
4'hc: H = 8'hc6; //顯示c
4'hd: H = 8'ha1; //顯示d
4'he: H = 8'h86; //顯示e
4'hf: H = 8'h8e; //顯示f
default: H =8'hff; //全滅
endcase
end
endmole
Ⅱ 用VHDL語言編寫程序：可逆的60進制計數器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT60 IS
PORT(CH,CLK,EN:IN STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
COUT:OUT STD_LOGIC);
END ENTITY CNT60;
ARCHITECTURE ONE OF CNT60 IS
BEGIN
PROCESS(CLK,EN,CH)
VARIABLE dd: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF EN='1' THEN
IF CH='1' THEN
IF dd<60 THEN dd:=dd+1;
ELSE dd:="000000";
END IF;
IF dd=60 THEN COUT<='1';
ELSE COUT<='0';
END IF;
ELSE IF dd>0 THEN dd:=dd-1;
ELSE dd:="111100";
END IF;
IF dd=0 THEN COUT<='1';
ELSE COUT<='0';
END IF;
END IF;
END IF;
END IF;
DOUT<=dd;
END PROCESS;
END ARCHITECTURE ONE;
--EN為使能信號，高電平有效，CH可以選擇，為1時進行加，為0時進行減。
Ⅲ 用VHDL語言編寫BCD碼60進制加法計數器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT60 IS
PORT(
CLK,EN,CR :IN STD_LOGIC;
LD :IN STD_LOGIC;
D :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CO : OUT STD_LOGIC;
Q :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CNT60;
ARCHITECTURE a OF CNT60 IS
SIGNAL QN :STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CO<='1' WHEN(QN=X"59" AND EN='1')
ELSE'0';
PROCESS(CLK,CR)
BEGIN
IF (CR='0')THEN
QN<=X"00";
ELSE
IF (CLK'EVENT AND CLK='1') THEN
IF (LD='0') THEN
QN<=D;
ELSIF(EN='1') THEN
IF QN(3 DOWNTO 0)=9 THEN
QN(3 DOWNTO 0)<="0000";
IF QN(7 DOWNTO 4)=5 THEN
QN(7 DOWNTO 4)<="0000";
ELSE
QN(7 DOWNTO 4)<= QN(7 DOWNTO 4)+1;
END IF;
ELSE
QN(3 DOWNTO 0)<= QN(3 DOWNTO 0)+1;
END IF ;
END IF;
END IF ;
END IF;
END PROCESS;
Q<=QN;
end a;
Ⅳ 用vhdl程序設計一個60進制（帶進位輸出）和12進制加法計數器（帶進位輸出）
請問要的是加法器還是計數器？60進制？還是60位寬？
Ⅳ 用verilog 寫一個 將十六進制數轉換十進制數的程序 和將 十進制數轉換成十六進制的程序
十六進制-->十進制：其實就是十六進制-->BCD，可參考http://wenku..com/view/313907020740be1e650e9a3d.html
我寫的代碼：
mole Bin2BCD16(A, B);
input [15:0] A;
output [19:0] B;
wire [3:0] c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13;
wire [3:0] c14, c15, c16, c17, c18, c19, c20, c21, c22, c23;
wire [3:0] c24, c25, c26, c27, c28, c29, c30;
wire [3:0] c31, c32, c33, c34;
wire [3:0] d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13;
wire [3:0] d14, d15, d16, d17, d18, d19, d20, d21, d22, d23;
wire [3:0] d24, d25, d26, d27, d28, d29, d30;
wire [3:0] d31, d32, d33, d34;
assign d1 = {1'b0, A[15:13]};
assign d2 = {c1[2:0], A[12]};
assign d3 = {c2[2:0], A[11]};
assign d4 = {c3[2:0], A[10]};
assign d5 = {c4[2:0], A[9]};
assign d6 = {c5[2:0], A[8]};
assign d7 = {c6[2:0], A[7]};
assign d8 = {c7[2:0], A[6]};
assign d9 = {c8[2:0], A[5]};
assign d10 = {c9[2:0], A[4]};
assign d11 = {c10[2:0], A[3]};
assign d12 = {c11[2:0], A[2]};
assign d13 = {c12[2:0], A[1]};
assign d14 = {1'b0, c1[3], c2[3], c3[3]};
assign d15 = {c14[2:0], c4[3]};
assign d16 = {c15[2:0], c5[3]};
assign d17 = {c16[2:0], c6[3]};
assign d18 = {c17[2:0], c7[3]};
assign d19 = {c18[2:0], c8[3]};
assign d20 = {c19[2:0], c9[3]};
assign d21 = {c20[2:0], c10[3]};
assign d22 = {c21[2:0], c11[3]};
assign d23 = {c22[2:0], c12[3]};
assign d24 = {1'b0, c14[3], c15[3], c16[3]};
assign d25 = {c24[2:0], c17[3]};
assign d26 = {c25[2:0], c18[3]};
assign d27 = {c26[2:0], c19[3]};
assign d28 = {c27[2:0], c20[3]};
assign d29 = {c28[2:0], c21[3]};
assign d30 = {c29[2:0], c22[3]};
assign d31 = {1'b0, c24[3], c25[3], c26[3]};
assign d32 = {c31[2:0], c27[3]};
assign d33 = {c32[2:0], c28[3]};
assign d34 = {c33[2:0], c29[3]};
Bin2BCD_Add3 m1(d1, c1);
Bin2BCD_Add3 m2(d2, c2);
Bin2BCD_Add3 m3(d3, c3);
Bin2BCD_Add3 m4(d4, c4);
Bin2BCD_Add3 m5(d5, c5);
Bin2BCD_Add3 m6(d6, c6);
Bin2BCD_Add3 m7(d7, c7);
Bin2BCD_Add3 m8(d8, c8);
Bin2BCD_Add3 m9(d9, c9);
Bin2BCD_Add3 m10(d10, c10);
Bin2BCD_Add3 m11(d11, c11);
Bin2BCD_Add3 m12(d12, c12);
Bin2BCD_Add3 m13(d13, c13);
Bin2BCD_Add3 m14(d14, c14);
Bin2BCD_Add3 m15(d15, c15);
Bin2BCD_Add3 m16(d16, c16);
Bin2BCD_Add3 m17(d17, c17);
Bin2BCD_Add3 m18(d18, c18);
Bin2BCD_Add3 m19(d19, c19);
Bin2BCD_Add3 m20(d20, c20);
Bin2BCD_Add3 m21(d21, c21);
Bin2BCD_Add3 m22(d22, c22);
Bin2BCD_Add3 m23(d23, c23);
Bin2BCD_Add3 m24(d24, c24);
Bin2BCD_Add3 m25(d25, c25);
Bin2BCD_Add3 m26(d26, c26);
Bin2BCD_Add3 m27(d27, c27);
Bin2BCD_Add3 m28(d28, c28);
Bin2BCD_Add3 m29(d29, c29);
Bin2BCD_Add3 m30(d30, c30);
Bin2BCD_Add3 m31(d31, c31);
Bin2BCD_Add3 m32(d32, c32);
Bin2BCD_Add3 m33(d33, c33);
Bin2BCD_Add3 m34(d34, c34);
assign B = {c31[3], c32[3], c33[3], c34[3:0], c30[3:0], c23[3:0], c13[3:0], A[0]};
endmole
////////////////////////////////////////////////////////////////////////////////
mole Bin2BCD_Add3(in4, out4);
input [3:0] in4;
output reg [3:0] out4;
always @(in4)
(in4)
4'b0000: out4 <= 4'b0000;
4'b0001: out4 <= 4'b0001;
4'b0010: out4 <= 4'b0010;
4'b0011: out4 <= 4'b0011;
4'b0100: out4 <= 4'b0100;
4'b0101: out4 <= 4'b1000;
4'b0110: out4 <= 4'b1001;
4'b0111: out4 <= 4'b1010;
4'b1000: out4 <= 4'b1011;
4'b1001: out4 <= 4'b1100;
default: out4 <= 4'b0000;
endcase
endmole
////////////////////////////////////////////////////////////////////////
十進制---->十六進制:
我一般都是直接使用乘法：B[15:0]=A[23:16]*100+A[15:8]*10+A[7:0]，因為現在的編譯器（如Quartus II）都支持
或者也可以使用移位運算實現，例如：
乘以100可以寫為：
a<<6+a<<5+a<<2
乘以10可以寫為：
a<<3+a<<1
Ⅵ 如何用VHDL語言編寫60進制減法計數器
你最好把各埠的用處說明一下。
主要的問題是：你的F定義為 STD_LOGIC_VECTOR(5 DOWNTO 0)
可在使用中只給出了4位的數據。
好好再考慮考慮
Ⅶ 用verilog hdl 語言編寫數字鍾源程序，解碼器，60，24進制，選擇器，分頻器代碼都寫好怎麼把它們弄到一起
做一個top mole ，在此mole里例化上述幾個子模塊。但是你需要確定top的輸入輸出信號，非埠信號但是子模塊之間相互連接的線定義為wire型。
Ⅷ 急求用hdl語言編寫六十進制計數器
mole counter(clk，seg7_1,seg7_0);
input clk;
output[3:0] seg7_1,seg7_0;
output cin；//進位信號
reg[3:0] seg7_1,seg7_0;
reg[3:0] data1,data0;
always@(posedge clk)
begin
if(data0<4'b1001)
begin
data0<=data0+4'b1;
cin<=1'b0;
end
else
begin
data0<=4'b0;
if(data1<4'b0101)
data1<=data1+4'b1;
else
begin
data1<=4'b0;
cin<=1'b1;
end
end
end
//以下為顯示程序，數碼管假設為共陰極；
always@(data1)
begin
case(data1)
4'b0000:seg7_1=7'b1111110;
4'b0001:seg7_1=7'b0110000;
4'b0010:seg7_1=7'b1101101;
4'b0011:seg7_1=7'b1111001;
4'b0100:seg7_1=7'b0110011;
4'b0101:seg7_1=7'b1011011;
default：_1=7'b0000000;
endcase
end
always@(data0)
begin
case(data0)
4'b0000:seg7_0=7'b1111110;
4'b0001:seg7_0=7'b0110000;
4'b0010:seg7_0=7'b1101101;
4'b0011:seg7_0=7'b1111001;
4'b0100:seg7_0=7'b0110011;
4'b0101:seg7_0=7'b1011011;
4'b0110:seg7_0=7'b1011111;
4'b0111:seg7_0=7'b1110000;
4'b1000:seg7_0=7'b1111111;
4'b1001:seg7_0=7'b1111011;
default：seg7_0=7'b0000000;
endcase
end
endmole